Basics of Memory Testing in VLSI Memory BIST
Memory is a very important component in the VLSI Semiconductor industry. In VLSI Circuits memories play a key role in storing huge data. Memory testing in VLSI using Algorithms and Patterns efficiently is important. Built in self test, self diagnosis, redundancy analysis and self repair. Various test algorithms which helps in testing of memories such as BIST compiler and BIST for RAM in Seconds. Memory faults and basics of checkerboard algorithm and march tests or algorithm will be discussed.
Table of Contents
1. Basic Introduction to Memory Testing
2. Basics of Memory Architecture
3. Fault Models in the memory cell array in Memory Testing
4. Basics of March Testing Algorithms and March Patterns in Memory Testing
5. Basics of MSCAN — Memory Scan Algorithm in Memory Testing
6. Basic Checkerboard Algorithm or Patterns in Memory Testing
7. Basics of March Test — bit-oriented March C algorithm in Memory Testing
8. Basic Faults Simulator in Memory Testing — RAMSES
9. Memory BIST (Built In Self Test) Model in Memory Testing
10. Conclusion to Memory Testing
1. Basic Introduction to Memory Testing
In the current situation the world is producing large amount of data which needs to stored in the memories. So memory technology is a growing technology in the semiconductor market. Understanding and improving the memory testing in VLSI is very important because they don’t have the logic circuits or any sequential elements like flops in them.
We have to have separate techniques, test strategies and methodologies for memory testing as they don’t have similar fault models and scan design techniques cannot be reused here. In short we cannot apply regular DFT techniques in the memory. Different fault models such as Stuck at fault, Stuck open fault, Transient faults, Data retention faults, Coupling faults, and Read disturb faults with their respective notations.
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2. Basics of Memory Architecture
An architecture of a memory model constitutes of array of memory cells. The array of memory cells are in the two dimensional form. A full address as fed to memory through address bus to row decoder and column decoder. Row decoder decodes the address and enables the rows based on the address. Similarly the Column decoder decoder the address from the bus to enable associated column cell arrays. Further memory cell is connected to A sense amplifier, which senses the data stored in the memory cell array amplify it and sends the data out.
As shown in the above memory model the intended data can be written into the memory or the data to be read out from the memory. The Read or Write enable signal is passed to the special circuitry to perform the memory operations.
We need to test the memory whether the correct data is being written or read out of the memory which is an important task. Basic and Typical examples of a memory is 1T DRAM and 6T SRAM. Sense amplifier plays a very crucial role and amplifying the data by considering the threshold for logic 1 and logic 0. The performance of the memory is analyzed based on how many clock cycles are required to write the data into the cell and clock cycles required to read the data out of the cell.
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3. Basic Fault Models in the memory cell array in Memory Testing
One needs to understand the various fault models used in the memory testing unlike fault models in the DFT of regular combinational circuits and sequential circuits(That is fault models in this case are differently analyzed as memories don’t have logic gates).
Before understanding the fault models we need to understand the notations
1. An up arrow ↑ denotes the rising transition during write operation.
2. A down arrow ↓ denote the falling transition during read operation.
3. An up/down arrow denotes either rising or falling transition.
4. Reversed A ∀ denotes any operation at the cell.
5. <S/F> denotes the operation activating the fault upon the faulty value of the memory cell.
Now let us list out the fault models in the memory testing,
1. SAF — Stuck at fault
Here there can be two faults, a stuck at 1 fault and a stuck at 0 fault. The notation for these can be, for stuck at 0 its < ∀/0 > which says for any operation on the cell, the cell response is 0 only. And for stuck at 1 its < ∀/1 > which says for any operation on the cell, the cell response is 0 only.
2. SOF — Stuck open fault
A stuck open fault occurs when there is discontinuity in a word line or a switch got permanently open.
3. TF — Transient Faults
Here there can be two faults, a rising transient fault and a falling transient fault. The notation for these can be, for rising transient fault its < ↑/0 > which says for rising operation of the cell, the cell response is 0 only which has to 1. And for falling transient fault its < ↓/1 > which says for falling operation of the cell, the cell response is 1 only which has to be 0.
4. DRF — Data Retention Fault
This kind of fault model arises if a cell become incapable to hold the data or retain the data for a specified period of time. here the memory cell loses its data spontaneously and not because READ or WRITE operations.
5. CF — Coupling faults
There are three kinds of coupling faults
1. CFin — Inversion Coupling fault, This kind of fault occurs when one cell transition leads to inversion of other cell content.
2. CFid — Idempotent Coupling fault, This kind of fault occurs when one cell transition leads to a constant value either 1 or 0 in other cell content.
3. CFst — State Coupling Faults, — Here the coupled cell is forced to a particular value only if the coupling cell is in this state; <0;0/1>, <1;0/1>, <0;1/0>, or <1;1/0>.
6. RDF — Read Disturb Faults
This kind of fault occurs during read operation. If the cell value is getting continuously flipped during the read operation we say it as Read disturb fault (RDF).
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